Etsoi with reduced extension resistance

ABSTRACT

A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

TECHNICAL FIELD

The present disclosure relates to silicon-on-insulator (SOT),particularly extremely thin silicon-on-insulator (ETSOI), and FinFETsemiconductor devices with reduced extension resistance. The presentdisclosure is particularly applicable to semiconductors for 22 nanometer(nm) node devices and beyond.

BACKGROUND

The integration of hundreds of millions of circuit elements, such astransistors, on a single integrated circuit necessitates furtherdramatic scaling down or micro-miniaturization of the physicaldimensions of circuit elements, including interconnection structures.Micro-miniaturization has engendered a dramatic increase in transistorengineering complexity, such as the inclusion of lightly doped drainstructures, multiple implants for source/drain regions, silicidation ofgates and source/drains, and multiple sidewall spacers, for example.

The drive for high performance requires high speed operation ofmicroelectronic components requiring high drive currents in addition tolow leakage, i.e., low off-state current, to reduce power consumption.Metal gate electrodes have evolved for improving the drive current byreducing polysilicon depletion. However, simply replacing polysilicongate electrodes with metal gate electrodes may engender issues informing the metal gate electrode prior to high temperature annealing toactivate the source/drain implants, as at a temperature in excess of900° C. This fabrication technique may degrade the metal gate electrodeor cause interaction with the gate dielectric, thereby adverselyimpacting transistor performance.

Replacement gate techniques have been developed to address problemsattendant upon substituting metal gate electrodes for polysilicon gateelectrodes. For example, an amorphous silicon (a-Si) or polysilicon gateis used during initial processing until high temperature annealing toactivate source/drain implants has been implemented. Subsequently, thepolysilicon is removed and replaced with a metal gate.

For improving low off-state leakage current, due to the fundamentallysuperior short channel control characteristics, ETSOI and FinFET are thebest candidates for complementary metal-oxide-semiconductors (CMOS)beyond the 22 nm node. As illustrated in FIG. 1, an ETSOI semiconductordevice begins with an ETSOI substrate comprising a silicon substrate101, a buried oxide layer 103, and a thin silicon layer 105. A gateelectrode 107 (including, from top to bottom, silicon nitride (SiN) cap109, a-Si layer 111, and gate oxide layer 113) is patterned on thesilicon layer of the ETSOI substrate. The silicon layer thickness istypically between about 6 nm and about 8 nm.

Adverting to FIG. 2A, during the patterning of gate electrode 107, theregion 201 immediately adjacent to gate 107 is eroded by about 1 nm bythe overetch process needed to insure that no gate-stack residual leftin the non-gated area. Then, in defining spacers 203, illustrated inFIG. 2B, the ETSOI is thither thinned by about 1 to about 2 nm from thespacer etch/strip/clean steps, i.e., when the resist is stripped posthalo extension implants. This causes very thin “bottle-neck” ETSOIextension regions 205 that have a high extension resistance (R_(ext))that is a times higher than a conventional SOI or bulk CMOS.

An approach to mitigate the high ETSOI R_(ext) is to form a raisedsource/drain 207 on the ETSOI by an epitaxial growth process. However,since the raised source/drain epitaxial growth does not change thesilicon thickness at the thinnest portion of the extension, under thespacers 203 that separate the gate electrode from the source/drainepitaxial growth, the “bottle-neck” region cannot be remedied merely byforming raised source/drain 207. R_(ext) is still dominated by theextension region resistance. High R_(ext) limits the application ofETSOI to low power applications. In order to enable ETSOI for highperformance logic devices, the R_(ext) must be significantly reduced.

A need therefore exists for methodology enabling the formation of an SOIsemiconductor device which is compatible with high-k metal gateintegration and which has low off-state leakage current and reducedR_(ext), and for the resulting device.

SUMMARY

An aspect of the present disclosure is an improved method of fabricatinga semiconductor exhibiting improved short channel effects and reducedextension.

Another aspect of the present disclosure is a semiconductor exhibitingimproved short channel effects and reduced extension resistance.

Additional aspects and other features of the present disclosure will beset forth in the description which follows and in part will be apparentto those having ordinary skill in the art upon examination of thefollowing or may be learned from the practice of the present disclosure.The advantages of the present disclosure may be realized and obtained asparticularly pointed out in the appended claims.

According to the present disclosure, some technical effects may beachieved in part by a method of fabricating a semiconductor, the methodcomprising: forming an SOI substrate; epitaxially forming asilicon-containing layer on the SOI substrate; and forming a gateelectrode on the epitaxially formed silicon-containing layer.

Aspects of the present disclosure include the SOI substrate comprising athin layer of silicon, as at a thickness of about 6 nm to about 8 nm, ona silicon substrate, with a buried oxide layer (BOX) therebetween.Additional aspects include removing the gate electrode and forming areplacement gate electrode. Other aspects include forming a first spaceron each side of the gate electrode. Further aspects include formingraised source/drain regions adjacent each first spacer. Another aspectincludes forming the source/drain regions as faceted source/drainregions. Other aspects include forming a second spacer on each firstspacer; and forming a silicide on the source/drain regions. Anotheraspect includes removing the gate electrode, thereby exposing a portionof the silicon-containing layer; and removing the exposed portion of thesilicon-containing layer. Additional aspects include removing theexposed portion of the silicon-containing layer by selectively etchingthe silicon-containing layer; and stopping on the SOI substrate. Otheraspects include forming a replacement gate electrode on the SOIsubstrate between the first spacers. Further aspects include thereplacement gate electrode comprising a high-k metal gate electrode.Additional aspects include forming the silicon-containing layer byepitaxially growing silicon germanium to a thickness of about 8 nm toabout 12 nm.

Another aspect of the present disclosure is a semiconductor devicecomprising: an SOI substrate; a gate electrode formed on the SOIsubstrate; an epitaxially formed silicon-containing layer on the SOIsubstrate, surrounding the gate electrode.

Aspects include the SOI substrate comprising a thin silicon layer, as ata thickness of about 6 nm to about 8 nm, on a silicon substrate with aBOX therebetween. Further aspects include a first spacer on thesilicon-containing layer on each side of the gate electrode and asource/drain region on the silicon-containing layer, adjacent each firstspacer. Another aspect includes the source/drain regions being raisedand faceted. Other aspects include a second spacer on each first spacer.Additional aspects include the gate electrode comprising a high-k metalgate electrode. Further aspects include the silicon-containing layercomprising silicon germanium at a thickness of about 8 nm to about 12nm.

Additional aspects and technical effects of the present disclosure willbecome readily apparent to those skilled in the art from the followingdetailed description wherein embodiments of the present disclosure aredescribed simply by way of illustration of the best mode contemplated tocarry out the present disclosure. As will be realized, the presentdisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects, all without departing from the present disclosure.Accordingly, the drawings and description are to be regarded asillustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawing and in whichlike reference numerals refer to similar elements and in which:

FIG. 1 schematically illustrates a conventional ETSOI semiconductordevice;

FIGS. 2A and 2B schematically illustrate ETSOI erosion during formationof an ETSOI semiconductor device; and

FIGS. 3 through 14 schematically illustrate sequential steps of a methodin accordance with an exemplary embodiment.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of exemplary embodiments. It should be apparent, however,that exemplary embodiments may be practiced without these specificdetails or with an equivalent arrangement. In other instances,well-known structures and devices are shown in block diagram form inorder to avoid unnecessarily obscuring exemplary embodiments.

The present disclosure addresses and solves the high R_(ext) problemattendant upon etching the gate stack, forming the gate spacers, andremoving the resist post halo implants in an SOI, particularly an ETSOI,semiconductor device. In accordance with embodiments of the presentdisclosure, an SOI semiconductor device is formed with an epitaxiallyformed silicon-containing layer on the SOI substrate. During areplacement gate process, the silicon-containing layer underlying thegate electrode is removed but the remaining silicon-containing layer isleft on the SOI substrate. Consequently, the Si layer of the SOIsubstrate is not eroded during gate patterning and spacer formation.Therefore, the extension thickness is increased, thereby reducing theextension resistance. In addition, ETSOI substrates may be employed,such that short channel effects are also improved.

Methodology in accordance with embodiments of the present disclosureincludes forming an SOI substrate, epitaxially forming asilicon-containing layer on the SOI substrate, and forming a gateelectrode on the epitaxially formed silicon-containing layer. Gatespacers, source/drain regions, and second spacers are sequentiallyformed on the silicon-containing layer. In accordance with embodimentsof the present disclosure, the gate electrode and underlyingsilicon-containing layer are removed and replaced with a high-k metalgate.

Still other aspects, features, and technical effects will be readilyapparent to those skilled in this art from the following detaileddescription, wherein preferred embodiments are shown and described,simply by way of illustration of the best mode contemplated. Thedisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects. Accordingly, the drawings and description are to be regardedas illustrative in nature, and not as restrictive.

A process for fabricating an SOI semiconductor, particularly an ETSOIsemiconductor, in accordance with an embodiment of the presentdisclosure begins by forming an SOI substrate comprising siliconsubstrate 301, BOX 303, and SOI layer 305, as illustrated in FIG. 3. SOIlayer 305 may be deposited to a thickness of about 6 nm to about 8 nm,thereby forming an ETSOI layer. Next, a silicon-containing layer 307,for example a SiGe layer, is epitaxially grown on ETSOI layer 305 to athickness of about 8 nm to about 12 nm, e.g., about 10 nm.Alternatively, carbon doped silicon (Si:C) may be grown on ETSOI layer305 to form silicon-containing layer 307. A protection layer 309, e.g.,an oxide layer, is then deposited on silicon-containing layer 307.

Adverting to FIG. 4, shallow trench isolation (STI) regions 401 areformed through protection layer 309, silicon-containing layer 307, andETSOI layer 305. To the sides of STI regions 401, n and p well implants403 a and 403 b are formed down to ETSOI layer 305. Both the STIformation and well implantation may be performed by conventionalprocesses. Then, protection layer 309 is stripped away.

As illustrated in FIG. 5, a gate dielectric layer 501 is deposited oversilicon-containing layer 307 and STI regions 401. Gate dielectric layer501 may, for example, be an oxide. A gate electrode layer 503, forexample a-Si or polysilicon, is then deposited over gate dielectric 501,followed by a capping layer 505, for example SiN. Gate electrodes arethen patterned. The resulting structure is shown in FIG. 6. The etchingof the gate electrodes causes an erosion of silicon-containing layer 307on each side of the gate electrode by about 1 nm (shown at 601).

Adverting to FIG. 7, spacers 701, e.g., SiN nitride spacers, aredeposited and etched. Halo and extension implantation andrecrystallization annealing are performed to form extensions 703. Asindicated at 705, additional erosion, e.g., about 1 nm to about 2 nm, ofsilicon-containing layer 307 occurs during formation of spacer 701.

Source/drain regions 801 are next formed on silicon-containing layer307. For example, as illustrated in FIG. 8, source/drain regions may beepitaxially formed with in-situ doping by conventional methods. As aresult, source/drain regions 801 are faceted and raised, and anundesirable parasitic capacitance between source/drain regions 801 andthe gate electrodes may be minimized Alternatively, implantation may beperformed to form source/drain regions 801.

As illustrated in FIG. 9, final spacers 901 are formed on spacers 701.The device then undergoes rapid thermal annealing (RTA) or laser scribeannealing (LSA), or a combination thereof, to densify the spacers and todiffuse the source/drain dopants. Silicide 903 may then be formed onsource/drain regions 801, or silicide 903 may be formed subsequent toforming replacement gates.

The replacement gate process begins in FIG. 10 by depositing andplanarizing dielectric layer 1001. Then, chemical mechanical polishing(CMP) is performed to expose gate electrode layer 503, as illustrated inFIG. 11.

Adverting to FIG. 12, gate electrode layer 503 is etched out, followedby the removal of gate dielectric 501. Next, silicon containing layer307 is selectively etched, stopping on ETSOI layer 305, as illustratedin FIG. 13.

As illustrated in FIG. 14, a high k gate dielectric 1401, e.g., ahafnium based oxide, a hafnium based oxynitride, or a hafnium-siliconoxynitride is deposited on ETSOI layer 305. Next, metal gate liner (notshown) is deposited, and metal 1403, e.g., titanium nitride, tantalumnitride, or aluminum nitride, is filled between spacers 701. The metalgate formation ends with metal CMP.

The embodiments of the present disclosure can achieve several technicaleffects, including minimized ETSOI thickness loss due to erosion causedduring gate patterning and spacer formation, reduced extensionresistance from the resulting increased extension thickness, andimproved short channel effects and shallow junction achieved by the lowETSOI thickness. The present disclosure enjoys industrial applicabilityin any of various types of highly integrated semiconductor devicesparticularly for 22 (nm) node devices and beyond.

In the preceding description, the present disclosure is described withreference to specifically exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of thepresent disclosure, as set forth in the claims. The specification anddrawings are, accordingly, to be regarded as illustrative and not asrestrictive. It is understood that the present disclosure is capable ofusing various other combinations and embodiments and is capable of anychanges or modifications within the scope of the inventive concept asexpressed herein.

What is claimed is:
 1. A method of fabricating a semiconductor device,the method comprising: forming an SOI substrate; epitaxially forming asilicon-containing layer on the SOI substrate; and forming a gateelectrode on the epitaxially formed silicon-containing layer.
 2. Themethod according to claim 1, wherein the SOI substrate comprises a thinsilicon layer on a silicon substrate with a buried oxide layer (BOX) inbetween, the thin silicon layer having a thickness of about 6 nm toabout 8 nm.
 3. The method according to claim 1, further comprising:removing the gate electrode; and forming a replacement gate electrode.4. The method according to claim 1, further comprising: forming a firstspacer on each side of the gate electrode.
 5. The method according toclaim 4, further comprising: forming raised source/drain regionsadjacent each first spacer.
 6. The method according to claim 5,comprising forming the source/drain regions as faceted source/drainregions.
 7. The method according to claim 5, further comprising: forminga second spacer on each first spacer; and forming a silicide on thesource/drain regions.
 8. The method according to claim 7, furthercomprising: removing the gate electrode, thereby exposing a portion ofthe silicon-containing layer; and removing the exposed portion of thesilicon-containing layer.
 9. The method according to claim 8, whereinremoving the exposed portion of the silicon-containing layer comprises:selectively etching the silicon-containing layer; and stopping on theSOI substrate.
 10. The method according to claim 8, further comprisingforming a replacement gate electrode on the SOI substrate between thefirst spacers.
 11. The method according to claim 10, wherein thereplacement gate electrode comprises a high-k metal gate electrode. 12.The method according to claim 1, comprising forming thesilicon-containing layer by epitaxially growing silicon germanium to athickness of about 8 nm to about 12 nm.
 13. A semiconductor devicecomprising: an SOI substrate; a gate electrode formed on the SOIsubstrate; an epitaxially formed silicon-containing layer on the SOIsubstrate, surrounding the gate electrode.
 14. The semiconductor deviceaccording to claim 13, wherein the SOI substrate comprises a thinsilicon layer on a silicon substrate with a buried oxide layer (BOX) inbetween, the thin silicon layer having a thickness of about 6 nm toabout 8 nm.
 15. The semiconductor device according to claim 13, furthercomprising: a first spacer on the silicon-containing layer on each sideof the gate electrode; and a source/drain region on thesilicon-containing layer, adjacent each first spacer.
 16. Thesemiconductor device according to claim 15, wherein the source/drainregions are raised and faceted.
 17. The semiconductor device accordingto claim 15, further comprising a second spacer on each first spacer.18. The semiconductor device according to claim 13, wherein the gateelectrode comprises a high-k metal gate electrode.
 19. The semiconductordevice according to claim 13, wherein the silicon-containing layercomprises silicon germanium at a thickness of about 8 nm to about 12 nm.20. A method of fabricating a semiconductor, the method comprising:forming an ETSOI substrate; epitaxially growing silicon germanium on theETSOI substrate to a thickness of about 8 nm to about 12 nm; forming agate electrode on the epitaxially formed silicon-containing layer;forming a first spacer on each side of the gate electrode; epitaxiallyforming a raised and faceted source/drain region on thesilicon-containing layer, adjacent each first spacer; removing the gateelectrode, thereby exposing a portion of the silicon-containing layer;selectively etching exposed portion of the silicon-containing layer,stopping on the ETSOI substrate; forming a high-k metal gate electrodeon the ETSOI substrate between the first spacers.